The present invention is generally directed to frequency synthesizers and, more particularly, to a PLL frequency synthesizer that may be finely tuned over a narrow range of frequencies.
There have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, radio frequency integrated circuits (RFIC), central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates in one chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a, television receiver, microprocessor, high-speed data transceiver, and the like).
In many integrated circuits, a phase-locked loop (PLL) frequency synthesizer generates many of the clock signals that drive the integrated circuit. Phase-locked loops (and delay-locked loops (DLLs)) are well known to those skilled in the art and have been extensively written about. The dynamic performance of the frequency synthesizer that generates clock signals depends on several parameters, including the natural frequency (Fn), the damping factor (DF), the crossover frequency (F0) and the ratio of the comparison frequency (Fc) to the crossover frequency. The performance of the frequency synthesizer also depends on the performance of the charge pump located in the PLL. The charge pump pulse timing jitter and pulse amplitude noise both contribute to synthesizer phase noise.
A common problem for a conventional PLL based on voltage-controlled oscillator (VCO) is the granularity with which the output frequency may be adjusted. Conventional PLLs contain a frequency divider (i.e., divide-by-N) block in the feedback loop. If the input frequency is F(in), then the output frequency is F(out)=N[F(in)]. However, N is typically an integer, so that increasing or decreasing N results in large increments or large decrements in the output frequency. A fractional N PLL may be implemented that changes in smaller increments. However, a fractional PLL requires complex circuitry and has a much slower response time.
Therefore, there is a need in the art for improved frequency synthesizers for use in generating reference frequency signals. In particular, there is a need in the art for a phase-locked loop (PLL) frequency synthesizer that can be finely tuned over a range of frequencies. More particularly, there is a need for a PLL frequency synthesizer that can be finely tuned and that has a fast response time.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an improved phase-locked loop (PLL) frequency synthesizer capable of being tuned in small step sizes. According to a first advantageous embodiment of the present invention, the phase-locked loop (PLL) frequency synthesizer comprises: i) a first PLL circuit comprising: i) a first feedforward frequency divider capable of receiving an F(in) reference signal having an F(in) frequency and generating an F1 signal having an F1 frequency, where F1=F(in)/P, ii) a first PLL core capable of receiving the F1 signal and generating an F2 signal having an F2 frequency, where F2=(P+xcex94p)F1, and iii) a first feedback frequency divider capable of receiving the F2 signal and generating a first feedback signal having a frequency F2/(P+xcex94p); and ii) a second PLL circuit comprising: i) a second feedforward frequency divider capable of receiving the F2 signal and generating an F3 signal having an F3 frequency, where F3=F2/(N+xcex94n), ii) a second PLL core capable of receiving the F3 signal and generating an F(out) signal having an F(out) frequency, where F(out)=(N)F3, and iii) a second feedback frequency divider capable of receiving the F(out) signal and generating a second feedback signal having a frequency F(out)/(N).
According to a second advantageous embodiment of the present invention, the phase-locked loop (PLL) frequency synthesizer comprises: i) a first PLL circuit comprising: i) a first feedforward frequency divider capable of receiving an F(in) reference signal having an F(in) frequency and generating an F1 signal having an F1 frequency, where F1=F(in)/(P+xcex94p), ii) a first PLL core capable of receiving the F1 signal and generating an F2 signal having an F2 frequency, where F2=(P)F1, and iii) a first feedback frequency divider capable of receiving the F2 signal and generating a first feedback signal having a frequency F2/(P); and
ii) a second PLL circuit comprising: i) a second feedforward frequency divider capable of receiving the F2 signal and generating an F3 signal having an F3 frequency, where F3=F2/(N),
ii) a second PLL core capable of receiving the F3 signal and generating an F(out) signal having an F(out) frequency, where F(out)=(N+xcex94n)F3, and iii) a second feedback frequency divider capable of receiving the F(out) signal and generating a second feedback signal having a frequency F(out)/(N+xcex94n).
In a PLL frequency synthesizer according to the principles of the present invention the feedforward and feedback divisor values in the first and second PLL circuits are spaced apart by a minimum amount and are modified in unison to maintain the minimum spacing. The minimum amounts, xcex94p and xcex94n, may be integers (1, 2, 3) or may be fractional amounts.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.